The present invention relates to an insulated gate type field effect transistor and, more particularly, to an insulated gate type field effect transistor having a large mutual conductance and used for an IC output buffer.
An example of a conventional insulated gate type field effect transistor is shown in FIG. 1. (Japanese Patent Publication No. 46-1058). The transistor comprises semiconductor substrate 1 and a plurality of source regions 2 and drain regions 3 formed in a surface region of substrate 1 in a matrix pattern to form an array. Four regions adjacent to each of source regions 2 are all drain regions 3, and four regions adjacent to each of drain regions 3 are all source regions 2. Therefore, when viewed in a direction of rows or columns of the array, regions 2 and 3 are alternately arranged. Source electrode layer 4 of Al (aluminium) formed on source regions 2 and drain electrode layer 5 of Al formed on drain regions 3 are arranged in such a manner that the extension directions of source and drain electrode layers 4 and 5 are diagonal with respect to a direction of the rows or columns of alternately arranged regions 2 and 3. In order to increase the mutual conductance gm of the transistor, the widths of electrode layers 4 and 5 must be maximized in terms of an allowable current of the electrode layers 4 and 5.
In the transistor, however, since electrode layers 4 and 5 are arranged diagonally to the rows or columns of alternately arranged regions 2 and 3, the widths of the source and drain electrode layers are reduced.
Another conventional insulated gate type field effect transistor as shown in FIG. 2 has been known. In this transistor, the configuration of contact holes 6 allowing communicating between the source and drain regions 2 and 3 and the wiring layer is a rectangle having long sides along a diagonal direction, thereby enlarging the contact area of source region 2 and source electrode layer 4 and the contact area of drain region 3 and drain electrode layer 5 so that contact resistances are reduced. However, in the transistor shown in FIG. 2, since electrodes layers 4 and 5 are arranged in a diagonal direction, the widths of the electrode layers cannot be formed sufficiently wide.
A further conventional insulated gate type field effect transistor shown in FIG. 3 has been known (Japanese Patent Disclosure (Kokai) No. 60-53085). In this transistor, the shape of contact holes 7 is a hexagon having two long sides along electrode layers 4 and 5, thereby reducing the contact resistances of source and drain regions 2 and 3 compared to that of the transistor shown in FIG. 2. However, also in this transistor, since electrode layers 4 and 5 are arranged in a diagonal direction, the electrode layers cannot be formed sufficiently wide.